The present invention relates in general to circuits and methods for analyzing the performance of digital logic circuits and, in particular, for measuring small propagation delays associated with digital logic circuits on large scale integration chips.
Two circuits and methods for measuring logic propagation delays of digital logic circuits are known in the prior art. These are methods which utilize a ring oscillator and a delayed Johnson counter.
In the ring oscillator method, an odd number of inverting logic gates are connected in sequence so as to form a closed loop. Since the number of devices is odd, the loop is unstable and oscillates. The observed frequency of oscillation is inversely proportional to the product of the average propagation delay of the logic gate times the number of logic gates used. One disadvantage to ring oscillator methods is that for testing very fast logic gates, a large number of gates are needed to reduce the oscillation frequency to a conveniently measurable frequency. In addition, high frequency test fixuring may still be required to measure the high oscillator frequency. Furthermore, in a performing delay versus fan out testing of the logic circuit, each inverting logic gate in the ring oscillator must be connected to similar gates equal in number to the proposed fan out loading. For large fan out testing of very fast gates, ring oscillator methods can require a very large test structure. A large test structure is undesirable because of statistical testing and yield considerations.
The delayed Johnson counter method relies on the fact that in operation of the digital logic circuit, the maximum frequency which can be introduced into the input of the counter and be observed to produce a toggling output is related to the average propagation delay of the device under test. Although the delayed Johnson counter may require fewer devices under test than does the ring oscillator method, high frequency test fixuring is still required. In addition, an external high frequency stimulus is also required.
A feature of the present invention is that lower frequency test fixuring may be utilized to determine the small propagation delay of the digital logic circuit. An advantage of the present invention is that the circuit for propagation delay measurement requires significantly fewer logic gates than the prior art ring oscillator method.
Another advantage of the present invention is that measurement to the output signal does not involve any harmonics of the output signal. Using the prior art ring oscillator method, for example, measurements of the output signal may actually be measurements of a harmonic of the output signal, thereby resulting in an erroneous analysis.